This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-184783, filed Jun. 19, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor laminated module, for example, comprising a plurality of laminated unit packages loaded with thin film semiconductor chips that are flip-chip connected with base substrates.
2. Description of the Related Art
An example of a constitution of a semiconductor laminated module according to the prior art will be described with reference to FIG. 4. FIG. 4 shows a sectional view of the prior art module. The semiconductor laminated module 41 is constituted by sequentially laminating, for example, three unit packages 42a, 42b and 42c. For example, a semiconductor chip 44a having a thickness of, for example, about 100 xcexcm is flip-chip connected to an upper surface of a base substrate 43a made of a glass-epoxy resin, and is bonded with a chip adhesive 45a such as a film-like thermosetting resin adhesive comprising, for example, an epoxy-based resin, whereby the unit package 42a as the lowermost layer is constituted. The semiconductor chip 44a is integrally bonded onto the base substrate 43a with a substrate adhesive 46a to complete the unit package 42a. A plurality of solder balls 47 are provided on a lower surface of the base substrate 43a, and they constitute connecting terminals to be connected with external devices.
On the lowermost unit package 42a, the unit package 42b as a second layer is laminated, and the unit package 42c as a third layer is further laminated. An upper surface of the unit package 42c of the third layer is covered with a base substrate 43d, thereby forming a laminated body of the semiconductor laminated module 41.
During the unit packages 42a, 42b and 42c are laminated sequentially, they are pressured together and heated, thus sequentially bonded using substrate adhesives 46a, 46b and 46c such as a Prepreg composed of a thermosetting resin adhesive such as an epoxy-based resin. Thus, a three-layer laminated body is formed as shown in FIG. 4.
The base substrate 43d provided on the uppermost unit package 42c as a cover is made from a glass-epoxy resin similarly to the base substrates 43a, 43b and 43c, and bonded with the substrate adhesive 46c. 
After the three unit packages 42a, 42b and 42c are laminated, through holes 48a and 48b are formed to penetrate the three-layer laminated body at both sides of the semiconductor chips 44a, 44b and 44c. Copper plating layers 49a and 49b are formed on the inside walls of the through holes 48a and 48b. 
When a heat-cycle test is performed on the semiconductor package 41 thus formed by laminating the unit packages 42a, 42b and 42c as shown in FIG. 4, the package 41 would be warped. This warp would cause detachment of each flip-chip connection portions between the base substrates 43a, 43b and 43c and the semiconductor chips 44a, 44b and 44c. This causes the adhesion of the laminated parts in the laminated body to be less reliable. In addition, when the semi-conductor chips 44a, 44b and 44c are in thin film forms, the semiconductor laminated package 41 is warped repeatedly in the heat-cycle test, which in some cases causes cracks in one or more of the semiconductor chips 44a to 44c. 
Considering causes of the above-mentioned prior art problems, it is evident that, after the semi-conductor chips 44a to 44c are flip-chip connected to the base substrates 43a to 43c, the warp is caused by stress occurred by a difference of thermal expansion amount between chip adhesives 45a to 45c, which are used as seal resin films for sealing lower sides of the semiconductor chips 44a to 44c, and the substrate adhesives 46a to 46c, which are used as seal resin films for sealing upper sides of the semiconductor chips 44a to 44c when the unit packages 42a to 42c are laminated. Further, it is evident that the warp is also caused by stress occurred by a difference of their elasticity modulus that varies with the temperature.
A semiconductor laminate module according to one aspect of the present invention comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive; a second adhesive for forming a laminated body by bonding the plurality of unit packages to each other; a third adhesive formed to cover upper surfaces of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive; and an uppermost substrate bonded to an uppermost unit package with the second adhesive.